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? usb cif/vga digital camera chipset STV0672-chipsetf-3-1.fm 29 november 2000 1/41 vv6410/vv6500 &STV0672 commercial in confidence the usb camera chipsets from stmicroelectronics are at the heart of a variety of products which have proven to be highly successful in a demanding marketplace. supported by comprehensive reference designs, technical backup and fully-featured software drivers, stmicroelectronics offers camera manufacturers the opportunity to benefit from rapid time to market with a product of proven quality. the vv6410/vv6500 are colormos tm digital cmos sensors that deliver outstanding picture quality. these cif/vga- resolution sensors have been created specifically to meet the standards required for personal video communications. both sensors feature automatic black and dark level calibration to ensure optimum image quality. the STV0672 co-processor receives image data from the sensor, that is processed, compressed and passed to the usb port. it incorporates a digital video processor engine, which performs automatic exposure, automatic gain control and automatic white balance, together with colour matrixing, gamma correction, peaking, automatic defect correction and noise cancellation logic. this data is then compressed to deliver high frame rates with minimum impact on image quality. the usb interface supports usb isochronous data transfer mode. this data transfer mode allows the user to specifiy the percentage of usb bandwidth to allocate to a usb device, thus allowing multiple cameras/other usb peripherals to be connected to a single usb hub. the chipset is backed by a fully-featured driver which provides a host of user-definable settings for optimum camera setup. the user interface supports a degree of customisation. stmicroelectronics offers a range of support services to guarantee product quality, including test specifications and test software. real-time video - up to 30fps cif,15fps vga multiple output video modes supported usb 1.1 compliant motion-jpeg compression isochronous usb data transfer automatic black and dark level calibration full vfw and twain driver support integrated voltage regulation pixel defect detection and correction minimal bom for complete usb camera programmable vendor id usb camera biometric identification toys and games pixel resolution 352 x 288 (cif) 640 x 480 (vga) array size 2.73mm x 2.04mm (cif) 4.89mm x 3.66mm (vga) exposure control automatic (to +82db) gain control automatic (to +30db) signal/noise ratio c.56db supply voltage 4.1v-5.25v dc (internally regulated) usb compatibility usb speci?ation v1.1 meets full power management requirements with no external components required supply current approx. 150ma (cif, 30fps) approx. 190ma (vga, 15fps) operating temperature (ambient) 0 o c - 40 o c (for extended temp. info please con- tact stmicroelectronics) package type vv6410c036: 36clcc vv6500c001: 48clcc STV0672: 64tqfp key features applications specifications
STV0672-chipsetf-3-1.fm 29 november 2000 commercial in confidence 2/41 table of contents 1. document revision history ............................................................................................ 3 2. introduction ................................................................................................................. ..... 4 2.1 STV0672 chipset general description ......................................................................................... .4 2.2 video processor (vp) ........................................................................................................ ............. 4 2.3 video compression (vc) engine ............................................................................................... .... 7 2.4 control processor........................................................................................................... ................ 8 2.5 v6410/vv6500 general description ............................................................................................ .. 8 2.6 power management ............................................................................................................ ........... 9 2.7 suspend mode ................................................................................................................ ............. 11 2.8 still image upload and remote wake-up.................................................................................... 11 3. external interfaces ......................................................................................................... 1 2 3.1 usb interface ............................................................................................................... ................ 12 3.2 usb vendor id (vid) and product id (pid) ................................................................................. 12 3.3 general purpose input and output signals, microport, digiport and external eeprom ............ 14 4. detailed specifications .................................................................................................. 15 4.1 STV0672 absolute max ratings ................................................................................................ .. 15 4.2 STV0672 ac/dc characteristics ............................................................................................... .. 16 4.3 vv6410 optical characterisation data........................................................................................ .18 4.4 vv6500 optical characterisation data........................................................................................ .19 4.5 vv6410 power consumption .................................................................................................... ... 20 4.6 vv6500 power consumption .................................................................................................... ... 20 4.7 digital input pad pull-up and pull-down strengths (vv6410 and vv6500) ................................ 21 5. pinout and pin descriptions .......................................................................................... 22 5.1 vv6410 pin details .......................................................................................................... ............ 22 5.2 vv6500 pin details .......................................................................................................... ............ 25 5.3 STV0672 pin details ......................................................................................................... ........... 28 6. package details .............................................................................................................. 31 6.1 vv6410 (36pin clcc)......................................................................................................... ......... 31 6.2 vv6500 (48pin clcc)......................................................................................................... ......... 32 6.3 STV0672 (64pin tqfp)........................................................................................................ ........ 33 7. vv6410/vv6500+STV0672 reference design .............................................................. 34 8. reference design and evaluation kits (rdk? and evk?)........................................ 38 9. design issues ................................................................................................................ .39 10. ordering details ............................................................................................................ .40
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 3/41 29 november 2000 1. document revision history revision date comments 1.0 28/06/00 first advance release 1.1 04/07/00 first preliminary release 2.0 11/07/00 add extra sensor information and move to new naming convention for datash- eets. 2.1 19/07/00 minor text corrections and additions dc parameters updated 3.0 28/07/00 the document presented in full release status. 0672 ac/dc parameters cor- rected. 3.1 24/10/00 eeprom serial data and serial clock pin assignments clari?d table 1 : document revision history
STV0672-chipsetf-3-1.fm introduction 29 november 2000 commercial in confidence 4/41 2. introduction 2.1 STV0672 chipset general description the STV0672 is a digital video processor requiring no external ram and minimum of passive support components to provide a complete usb camera. STV0672 accepts raw digital video data from a cif format cmos sensor (vv6410) or from a vga format cmos sensor (vv6500) and is capable of transferring the resulting ycbcr video data to a host pc over usb at rates up to 30 frames per second (cif) or 15 frames per second (vga). the STV0672 architecture consists of a number of separate functional blocks: video processor (vp) to include interface logic to sensor video compressor (vc) usb control block general purpose control the vp controls the vvvv6410/vv6500 sensor and processes the raw rgb pixel data into cif or qcif ycbcr images this ycbcr data is compressed by the vc. the usb control block transfers the compressed data to the host pc. system operation, responding to host requests and commands as well as performing sensor exposure control and colour balance is handled by the video processor (vp). 2.2 video processor (vp) 2.2.1 video processor/sensor interface the STV0672 video processor (vp) module provides formatted ycbcr 4:2:2-sampled digital video to the video compressor (vc) module at frame rates up to 30 frames per second. the vp also interfaces directly to the vv6410/vv6500 image sensors. the interface to the sensor incorporates: a 5-wire data bus sdata[4:0] for receiving both video data and embedded timing references. a 2-wire serial interface ssda,sscl to control the sensor (allow reconfiguration of the sensor registers). the sensor clock sclk. the sensor regulates the usb system power to 3v3 for both the sensor and the STV0672. the sensor requires one external simple transistor in conjunction with the internal regulator to provide current drive to be able to successfully power the complete camera system the sensor also provides a power-on-reset signal that is used to reset the STV0672. this power-on-reset signal also resets the sensor. the module supports usb suspend mode. the simplified block diagram shown below highlights STV0672? key functional blocks.
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 5/41 29 november 2000 figure 1 : block diagram of STV0672 video processor module 2.2.1 video processor functions STV0672 provides a master clock sclk to the camera module. each 10-bit pixel value generated by the sensor is transmitted across the 5wire, (the msbit of the databus is unused in the current application but it will support future sensors where a 12b it adc architecture may be used), databus sdata[4:0] as a pair of sequential 5-bit nibbles, most significant nibble first. codes representing the start and end frames and the start and end of lines are embedded within the video pixel data stream to allow the video processor receiver to synchronise with the video data which the sensor is generating. the video processing engine performs the following functions on incoming data full colour restoration at each pixel site from bayer-patterned input data matrixing/gain on each colour channel for colour purity peaking for image clarity gamma correction colour space conversion (including hue and saturation control) from raw rgb to ycbcr[4:2:2]. the 2-wire sensor serial interface (ssda and sscl) provides control of sensor configuration. figure 2 below gives a block overview of the vp module. 2.2.2 auto exposure and gain control control of the sensor exposure is automatically controlled by STV0672. sensor exposure is evaluated (and, where necessary compression engine motion jpeg video processor stream digiport d+ d- clocks + pll porb 12mhz xtal 8052 core rom microport i/f 10 15 STV0672 ram serial i/f to eeprom (gpio) (gpio) compressed data control + fifos ext. interrupts usb port vv6410 cif/vga sensor /vv6500 general purpose housekeeper functions including aec,agc and awb video data[4:0] sscl ssda porb sck suspend usb core/glue logic and command fifo? sda scl reset
STV0672-chipsetf-3-1.fm introduction 29 november 2000 commercial in confidence 6/41 modified) once per frame, where a frame consists of 2 video fields. the video fields are identical in length, that is they do n ot contain any of the half line detail of the analogue video standards like ccir or ntsc. two fields per frame are required by the internal sensor video timing model. integration time, sensor analogue gain and STV0672 digital gain are all used to control the overall exposure. the STV0672 exposure algorithm uses an asymptotic approach in calculating the change required in the present exposure value to approach the requested exposure target. 2.2.3 defect correction STV0672 automatically detects and corrects for pixel defects, without the need for any additional components or additional sensor calibration procedures. this greatly simplifies camera assembly and test, when compared with previous eeprom-based defect correction schemes. the pixel defect correction scheme in STV0672 ensures that vv6410+STV0672 and vv6500+STV0672 are ?efect free?chipsets. 2.2.4 interpolation the bayer pattern from the sensor provides under-sampled trichromatic data. interpolation up-samples these undersampled data streams to restore a bandlimited (effectively blurred) version of the original, using simple two-dimensional filtering template s. signal components aliased in the under-sampling process remain aliased after interpolation. the green channel (no longer containing notions of even and odd rows) is treated differently from red and blue, being interpolated into two output representations, one ?harper?(containing more high-frequency detail) than the other. the smoother of the two green signals is output along with red and blue to the matrix block. 2.2.5 unsharp masking subtraction of these two green representations creates an ?nsharp mask? which can be further processed before adding back into the main colour flow. the unsharp signal undergoes variable coring (a central thresholding operation for noise reduction) and intensity (gain operation on the cored signal). the strain parameter from the housekeeper acts as both a coring threshold and an attenuator on the user intensity setting, achieving a softening of image appearance in low-light conditions. figure 2 : STV0672 vp block diagram ram/data storage logic key === fpn vector fpn cancel input processor set-up registers defect map defect detect & correct line store (9x644x10) address gen control (all sub blocks) matrix ram rom qvga fifo gamma ycbcr encoder (644x14) (128x32) 4:2:2 house keeper (aec,agc, awb etc) + in out interpolation peaking
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 7/41 29 november 2000 2.2.6 matrixing this module performs a 3 x 3 matrix multiplication on the smooth rgb channels, to map pixel taking chromaticities onto nominal display chromaticities. depending on the characteristics, a general 3 x 3 matrix can effect the transformation; however we choose to decompose this matrix into the form m = ut, where u is a neutral-preserving matrix, each of whose rows add to unity, and t is a diagonal matrix of tilts, which form one component of the channel gains applied in the input processor. the combination of u and t are coded in such a way as to require the user provision of 9 integers; three for the tilts t and six for the off-diagona l components of u (on-diagonal coefficients are implicit in a re-ordered row computation). the strain parameter from the housekeeper and a specially-cored version of the unsharp mask signal control the damper; a variable which desaturates the effect of the matrix by attenuating off-diagonal components in the presence of noise (strain component, occurring in low ambient light) or bayer aliasing (unsharp component, occurring in image regions with high edge-content). 2.2.7 peaking the unsharp mask signal is added to each matrixed colour channel to compensate for edge information lost in bayer-pattern under-sampling and interpolation. 2.2.8 gamma correction gamma correction provides a non-linear distortion of data amplitudes required for various video communication standards, as well as cosmetic enhancement of image detail. 2.2.9 coder the coder module comprises a color-space convertor which takes rgb from the gamma module and produces luminance y and weighted colour-differences cb & cr. the data is now passed in ycbcr form to the video compression block. 2.3 video compression (vc) engine the video compression engine performs 3 main functions: up scaling of input ycbcr 4:2:2 video stream from the vp (typically to scale from qvga to cif image formats) compression and encoding of ycbcr stream into motion-jpeg (m-jpeg) format usb bandwidth monitoring figure 3 below gives a block overview of the vc module. the data stream from the vp can be upto vga size. the scaler in vc can downsize this image. once scaled the video stream is then converted into m-jpeg format. m-jpeg simply treats video as a series of jpeg still images. please note that the jpeg specific header information need not be transmitted in a mjpeg stream. the conversion is realised via a sequential dct (discrete cosine transform) with huffman encoding. after transfer over usb the m-jpeg stream will be decoded in the video-for-windows (vfw) device driver running on the host. the vc module is capable of compression ratios of up to 100:1 although clearly this is scene dependent. image framerate produced by the STV0672 chipset is fixed and furthermore the available usb bandwidth is also fixed (within the software driver). the vc module varies the compression ratio to match the fluctuating input video data rates, that vary according to scene dynamics, to the available usb bandwidth and required framerate. the final stage of the vc block manages the data transfer rate from the local vc fifo store to the usb core. STV0672 can perform this management automatically, by employing long-term (frame-level) and short-term (block-level) compression management. the former is achieved by varying a scalar quality-factor from frame to frame, to drive expected data rates upwards or downwards. the latter is achieved by truncating the zig-zag sequence of ac coefficients more or less severely according to how many preset thresholds of fifo usage have been crossed. as fifo usage approaches maximum, this truncation process reduces instantaneous data rates until stability is regained, at the cost of local loss of detail in the image. the latter pro cess is transparent to the decoder. statistics of threshold-crossing activity are subsequently used in the long-term quality setting decision.
STV0672-chipsetf-3-1.fm introduction 29 november 2000 commercial in confidence 8/41 2.4 control processor the embedded 8052 microprocessor core plays a very important role within the STV0672 controlling data flow through the major sub blocks within STV0672 as well as the i2c communications to reconfigure vp in line with requests from the device driver. 2.5 v6410/vv6500 general description the vv6410 sensor is a cif format, 352 x 288 pixels, cmos image sensor capable of outputting digital pixel data at frame rates, of up to 30 frames per second. the vv6500 sensor is a vga format, 640 x 480 pixels, cmos image sensor capable of outputting digital pixel data at frame rates, of up to 15 frames per second (in vga mode). both sensor arrays are covered by colour filter s. vv6410/vv6500 have on-chip 10-bit analogue to digital converters and are designed to interface directly to the STV0672 co- processor chip as described above. dct quantiser entropy coder usb fifo 8-line ram block ram auto squeeze huffman tables raster to block control row/col/zig-zag control quantisation tables figure 3 : STV0672 vc block diagram ram/data storage logic key === in out (stores yuv)
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 9/41 29 november 2000 2.5.1 image format the output image format is either cif (352 x 288 pixel array) or vga (640 x 480 pixel array). to provide the colour co-processor with the extra information it needs for interpolation at the edges of the vv6410/vv6500 pixel array, an additional border 2 pix els deep on all 4 sides of the array is enabled under serial interface control. the resulting image size of 356 x 292 pixels (or 64 4 x 484 pixels for vga) is the default power up state for this sensor. the pixel array is covered by a set of bayer pattern colour dyes, see figure 5 for details. . 2.6 power management all the power management for the chipset is controlled by the sensor. a series of on board voltage regulators regulate the incoming vbus supply to derive all the necessary power supplies required by the camera chipset. the chipset conforms to all power requirements specified by usb version 1.1. figure 4 : block diagram of vv6410/vv6500 image sensor (5-wire output) output format d[4:0] ssda sscl sck image format exposure control serial interface offset cancellation digital logic y- decoder vregs, audio amp., & refs photo diode array column adc readout analogue core structure x-decoder sram line store suspend figure 5 : bayer colourisation pattern green 1 blue green 2 red odd rows (5, 7, 9,...) even rows (4, 6, 8,...) odd columns (1,3,5,...) even columns (2, 4, 6,...)
STV0672-chipsetf-3-1.fm introduction 29 november 2000 commercial in confidence 10/41 blue green green red blue green green red 644 pixels 356 pixels 292 pixels 484 pixels figure 6 : image formats 4 3 2 1 6 8 7 5 6 5 1, 2, 3, 4, 5, 6,... ..., 649, 650, 651, 652 5, 6, 7, 8, 9, 10,... ..., 485, 486, 487, 488 144 pixels 96 pixels blue green green red 10 9 8 7 648 647 646 645 484 486 485 483 650 649 488 487 652 651 488 pixels 652 pixels blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red 324 pixels 244 pixels 160pixels 120 pixels
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 11/41 29 november 2000 2.7 suspend mode under the control of the suspend pin vv6410/vv6500 can be forced into an ultra low power mode. the sensor will consume less than 80 a of current while suspended and the STV0672 device will consume approximately 50 a. the total chipset consumption therefore is approximately 150 a. the sensor will enter suspend mode when the suspend pin has been driven high. the suspend mode is effectively identical to a power-on-reset - all the video timing blocks within the sensor are reset as are the contents of the serial interface, ther efore the user will have to perform a compete reconfiguration of the device on exitting suspend. 2.8 still image upload and remote wake-up the present STV0672 reference design includes 2 micro switches, identified as sw1 and sw2. two special functions are supported by these switches - image upload via a twain driver and remote wake up of the host. presently both of these features will be invoked by depressing sw1. if the camera/host is in standby mode then pressing sw1 will force the system to wake up. thereafter sw1 will control the uploading of still images to the host. it is important to not e that STV0672 must always be used in tethered mode, attached to a pc, and there is no local memory for image storage. mode description approx. module current suspend camera module in lowest power state. suspend has been asserted by host. the clock to sensor has been removed and all blocks within STV0672 have been powered down. c.100 a table 2 : STV0672 chipset power consumption
STV0672-chipsetf-3-1.fm external interfaces 29 november 2000 commercial in confidence 12/41 3. external interfaces 3.1 usb interface the usb interface is designed to be compliant with the version 1.1 of the usb specification. the STV0672 chipset solution is a high power device and is therefore suitable for connection to any usb port on a pc or on a self-powered hub. it will not function when connected to a bus-powered hub as there may be insufficient power available. the device fits into the device framework specified in chapter 9 of the usb specification as follows: the device supports a single high power configuration ( configuration 1 ). endpoint 0 is the default control endpoint and is always supported endpoint 0 supports all of the usb commands required by the device framework. vendor specific commands on endpoint 0 are used for all device control. configuration 1 supports a single interface (interface 0 ) interface 0 supports 8 alternate settings ( alternates 0-7 ) the alternate settings support between 0 and 2 additional endpoints. endpoint 1 is used for isochronous transfer of image data endpoint 3 is used for transferring status information, e.g. state of a hardware button. the endpoints are configured as follows in the alternate settings: the best and most consistent performance in terms of image quality will always be obtained in the highest bandwidth setting (alternate 7). under some circumstances it may not be possible for the host to allocate this amount of usb bandwidth to the device. the isochronous settings reserve varying quantities of bandwidth - from 10% to 85% of usb bandwidth. the lower settings will give poor image quality due to heavy compression applied to maintain high framerate streaming of image data, but at the same time will leave more bandwidth free for other usb devices. this may be more desirable if more than one camera is to be used, or if there are other isochronous peripherals connected. the device driver allows the user to specify the maximum bandwidth they wish to allocate to data transfer from the device. if the maximum specified by the user is not available, perhaps because another isochronous device has already reserved that bandwidth, then lower alternates will be tried until one succeeds. benchmark testing of the STV0672 indicates that 30fps cif video (compressed) can be accomodated in 50% of usb bandwidth. 3.2 usb vendor id (vid) and product id (pid) all usb devices will report a vid and pid as part of a standard device descriptor. the vid and pid for STV0672 are configured alternate setting endpoint1 (isochronous) endpoint3 (interrupt) 0 not present not present 1 not present 8 bytes/packet; 1 packet/8 frames 2 128 bytes/packet; 1 packet/frame 8 bytes/packet; 1 packet/8 frames 3 384 bytes/packet; 1 packet/frame 8 bytes/packet; 1 packet/8 frames 4 640 bytes/packet; 1 packet/frame 8 bytes/packet; 1 packet/8 frames 5 768 bytes/packet; 1 packet/frame 8 bytes/packet; 1 packet/8 frames 6 896 bytes/packet; 1 packet/frame 8 bytes/packet; 1 packet/8 frames 7 1023 bytes/packet; 1 packet/frame 8 bytes/packet; 1 packet/8 frames table 3 : endpoint alternate settings
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 13/41 29 november 2000 by the state of the digiport bus bits. the digiport also controls the device current consumption that is reported to the host a t device enumeration. the current reference design for the STV0672-chipset has digiport[7:0] connected to vss, thus the vid and pid are 16?0553 and 16?0100 respectively. digiport bit slice function [3:0] con?ures the ls nibble of the pid [5:4] master vid/pid select [7:6] power setting table 4 : basic digiport con?uration digiport[3:0] pid ls nibble 4?0000 4?0000 4?0001 4?0001 4?0010 4?0010 4?0011 4?0011 4?0100 4?0100 4?0101 4?0101 4?0110 4?0110 4?0111 4?0111 4?1000 4?1000 4?1001 4?1001 4?1010 4?1010 4?1011 4?1011 4?1100 4?1100 4?1101 4?1101 4?1110 4?1110 4?1111 4?1111 table 5 : digiport ls nibble con?uration digiport[5:4] vid/pid reported 2?00 16?0553/16?010x 1 2?01 16?0553/16?011x 2 2?10 16?0553/16?012x 3 table 6 : master vid/pid selection
STV0672-chipsetf-3-1.fm external interfaces 29 november 2000 commercial in confidence 14/41 3.3 general purpose input and output signals, microport, digiport and external eeprom the present datasheet makes no attempt to discuss some of the peripheral functions that could be offered with the STV0672 chipset. it may be appropriate for such features to be included in a later version of this datasheet. if any customers require more information on these features please contact stmicroelectronics. 2?11 16?0553/16?013x 4 1. the ??ls nibble of the pid is de?ed by the value from table 5 above 2. the ??ls nibble of the pid is de?ed by the value from table 5 above 3. the ??ls nibble of the pid is de?ed by the value from table 5 above 4. the ??ls nibble of the pid is de?ed by the value from table 5 above digiport[7:6] current consumption reported 2?00 250ma 2?01 300ma 2?10 400ma 2?11 500ma table 7 : device power consumption indicator digiport[5:4] vid/pid reported table 6 : master vid/pid selection
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 15/41 29 november 2000 4. detailed speci?ations 4.1 STV0672 absolute max ratings description range unit operating temperature 0 to 70 o c storage temperature -50 to 150 o c voltage on usb d+/d- 0 - vdd v
STV0672-chipsetf-3-1.fm detailed specifications 29 november 2000 commercial in confidence 16/41 4.2 STV0672 ac/dc characteristics parameter description min typ max units comments vdd primary STV0672 power supply 3.0 3.3 3.6 v vddu power supply for on-chip usb transceiver 3.0 3.3 3.6 v i suspend STV0672 suspend mode current 20 a vdd at 3v3 i active STV0672 active, high power mode current 150 ma vdd at 3v6 when streaming vga video at 15fps. i active STV0672 active, low power mode current 22 ma vdd at 3v6 with vv6410 sensor 32 ma vdd at 3v6 with vv6500 sensor i leakage leakage current +/-2 a v ilu usb differential pad d+/d- input low 0.8 v v ihu usb differential pad d+/d- input high (driven) 1 1. these parameters are not measured but stmicroelectronics will guarantee the published values. 2.0 v v ihuz usb differential pad d+/d- input high (?ating) 2 2. these parameters are not measured but stmicroelectronics will guarantee the published values. 2.7 3.6 v v di usb differential pad d+/d- input sensitivity 3 3. v di = [(d+) - (d-) 0.2 v v cm usb differential pad d+/d- common mode volt- age 4 4. v cm includes v di range. 0.8 2.5 v v olu usb differential pad d+/d- output low voltage 5 5. these parameters are not measured but stmicroelectronics will guarantee the published values. 0.0 0.3 v v ohu usb differential pad d+/d- output high voltage 6 6. these parameters are not measured but stmicroelectronics will guarantee the published values. 2.8 3.6 v v ohu usb differential pad d+/d- output high voltage 7 7. these parameters are not measured but stmicroelectronics will guarantee the published values. 2.8 3.6 v v crs usb differential pad d+/d- output signal cross over voltage 8 8. these parameters are not measured but stmicroelectronics will guarantee the published values. 1.3 2.0 v v il cmos input low voltage 0.35vdd v v ih cmos input high voltage 0.65vdd v v t threshold point 1.65 v v oh output high voltage 2.4 v v ol output low voltage 0.4 v clk in input clock frequency 9 9. although the device is tested at an upper limit of 24mhz, the usb speci?ation version 1.1 states that the maximum clock input frequency is 12mhz . 12 24 mhz
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 17/41 29 november 2000 4.3 chipset vv6410/vv6500+STV0672 4.1 vv6410 ac/dc speci?ation table 9 : vv6410 dc speci?ation mode of operation vv6410+STV0672 vv6500+STV0672 standby mode camera module in lowest power state. suspend has been asserted by host. the clock to sensor has been removed and all blocks within STV0672 have been powered down. c.100 ? c.100 ? start-up mode STV0672 is in low power mode. fast clocks enabled allowing STV0672 to process commands from host pc. sen- sor and video processor module are held in reset c.22ma c.32ma active mode all STV0672 modules and sensor are enabled with video data being trans- ferred to host pc. c.140ma c.190ma table 8 : vv6410/vv6500+STV0672 chipset current consumption parameter comment units image format 356 x 292 pixels (cif) - pixel size 7.5 x 6.9 m technology 0.5 m 3 level metal cmos - array format cif - exposure control range 81 (minimum exposure period 3 s and maximum exposure period is 33ms) 1 1. we assume cif (30fps) mode, input clock of 16mhz and internal clock divisor of 1. db supply voltage 3.0-6.0 dc +/-10% v operating temp. range 0 - 40 o c v ol_max 2 2. this will be worst case reading. device outputs had signi?ant capacitive loading and supply voltage reduced to 2v7 0.512 v v oh_min 3 3. this will be worst case reading. device outputs had signi?ant capacitive loading and supply voltage reduced to 2v7 2.054 v v i_maxl 4 4. this will be worst case reading. device outputs had signi?ant capacitive loading and supply voltage reduced to 2v7 0.683 v v ih_min 5 5. this will be worst case reading. device outputs had signi?ant capacitive loading and supply voltage reduced to 2v7 2.237 v serial interface frequency range 0-100khz
STV0672-chipsetf-3-1.fm detailed specifications 29 november 2000 commercial in confidence 18/41 4.2 vv6500 ac/dc speci?ation table 10 : preliminary data for vv6500 4.3 vv6410 optical characterisation data parameter comment units image format 644 x 484pixels (vga) - pixel size 7.5 x 7.5 m technology 0.5 m 3 level metal cmos - array format vga - exposure control range 81 (minimum exposure period 3 s and maximum exposure period is 33ms) 1 1. we assume cif (30fps) mode, input clock of 16mhz and internal clock divisor of 1. db supply voltage 3.0-6.0 dc +/-10% v operating temp. range 0 - 40 o c v ol_max 2 2. this is worst case reading. device outputs had signi?ant capacitive loading and supply voltage reduced to 2v7 tba v v oh_min 3 3. this is worst case reading. device outputs had signi?ant capacitive loading and supply voltage reduced to 2v7 tba v v i_maxl 4 4. this is worst case reading. device outputs had signi?ant capacitive loading and supply voltage reduced to 2v7 tba v v ih_min 5 5. this is worst case reading. device outputs had signi?ant capacitive loading and supply voltage reduced to 2v7 tba v serial interface frequency range 0-100 khz optical parameter min typical max units dark current - 46 - mv/sec average sensitivity - 2.1 - v/lux.sec fixed pattern noise (fpn) - 1.74 - mv vertical fixed pattern noise (vfpn) - 1.2 - mv random noise - 1.17 - mv sensor snr - c.56 - db shading (gross) - 0.9 - mv table 11 : vv6410 optical characterisation data
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 19/41 29 november 2000 4.4 vv6500 optical characterisation data 4.4.1 noise parameters and dark current various noise parameters are measured on the 410 and 500 series sensors as follows: fixed pattern noise (fpn) vertical fixed pattern noise (vfpn) random noise fine shading gross shading the parameters will be described in more detail below along with the data produced by the characterisation programme. 4.4.2 blooming blooming is a phenomenon that does not affect cmos sensors in the same way as ccd imagers are afflicted. with a ccd blooming can cause an entire column/columns to flood and saturate. cmos imagers are however affected by a different type of saturation. if an intense light source, (e.g. maglite torch), is shone at very close proximity to the image sensor the pixel sampling mechanism will break down and rather than displaying a saturated white light a black image will occur. the 410 pixel architecture uses correlated double sampling (cds) to help reduce noise in the system. the pixel is read normally first, yielding the true integrated signal information, then the pixel is reset and very quickly read for a second time. this n ormally yields black information - as the pixel has had no exposure time - that can be subtracted from the signal from the first read. this subtraction will remove much of the noise from the pixel leaving only the useful signal information. in an example where a pixel has saturated in both the first and the second reads due to an intense light source. when the noise cancellation subtraction operation is then performed the result is close to zero signal from the pixel therefore resulting in t he displayed black image. we do not perform any test measurements for this phenomenon. 4.4.3 dark current this is defined as the rate at which the average pixel voltage increases over time with the device not illuminated. the dark current will be measured at a gain setting of 4 and a clock divisor of 16 at a fixed temperature and will be expressed in mv. 4.4.4 fixed pattern noise the fpn of an image sensor is the average pixel non-temporal noise divided by the average pixel voltage. the illumination optical parameter min typical max units dark current - tba - mv/sec average sensitivity - tba - v/lux.sec fixed pattern noise (fpn) - tba - mv vertical fixed pattern noise (vfpn) - tba - mv random noise - tba - mv sensor snr - tba - db shading (gross) - tba - mv table 12 : vv6500 optical characterisation data
STV0672-chipsetf-3-1.fm detailed specifications 29 november 2000 commercial in confidence 20/41 source will be white light that has been ir filtered, producing a diffuse uniform illumination at the surface of the sensor pac kage. the fpn will be calculated at coarse exposure settings of 0,10,150,250 and 302 with gain set to 1. 10 frames are grabbed and averaged to produce a temporally independent frame before each calculation. fpn will be expressed in mv. 4.4.5 vertical fixed pattern noise vfpn describes the spatial noise in an image sensor related to patterns with a vertical orientation. the vfpn is defined as the standard deviation over all columns of the average pixel voltage for each column determined at zero exposure and zero illumination. vfpn will be expressed in mv. 4.4.6 random noise random noise is the temporal noise component within the image. random noise will be expressed in mv. 4.4.7 shading this describes how average pixel values per ?lock?change across the image sensor array. for fine shading calculations the image sensor array is split into 30 pixel by 30 pixel blocks. an average value is then calculated for each block and the averag es are then compared across the whole device. the blocks are increased in size to 60 pixels by 60 pixels for the gross shading calculation. shading will be expressed in mv. 4.5 vv6410 power consumption 4.6 vv6500 power consumption table 13 : vv6410 current consumption in different modes operating condition current consumption low power mode current consumption 5.6ma sleep mode current consumption 1 1. estimated ?ures - this parameter was not measured during ?al characterisation 18ma suspend mode current consumption (with clkip disabled) 85ua normal operating mode current consumption 2 2. measured while device is clocked at 16mhz and streaming cif video at 30fps 26.2ma operating condition current consumption low power mode current consumption 7.6ma sleep mode current consumption 1 1. estimated ?ures - this parameter was not measured during ?al characterisation 18ma suspend mode current consumption (with clkip disabled) 74ua normal operating mode current consumption 2 2. measured while device is clocked at 24mhz and streaming vga video at 30fps 42ma (max)
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 21/41 29 november 2000 4.7 digital input pad pull-up and pull-down strengths (vv6410 and vv6500) pad type pads min current max current library pulldown suspend 35 a52 a library pullup sclk, sda, oeb 25 a42 a custom pullup resetb 66 a 250 a table 14 : pad pull-up/pull-down strengths
STV0672-chipsetf-3-1.fm pinout and pin descriptions 29 november 2000 commercial in confidence 22/41 5. pinout and pin descriptions 5.1 vv6410 pin details figure 7 : 36 pin clcc package pin assignment name pin number type description power supplies avss 10 gnd core analog ground and reference supplies. resetb d[0] lst/d[5] fst/d[6] vddcore/ vbus vbg vrt aoutp vddhi oeb clki 7 8 6 5 4 3 2 1 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 36 d[3] d[4] aud3v3 aoutn vbase avss 18 30 31 vbltw d[1] vid3v3 ain vsscore vssio sramvss d[2] qck sda suspend vddio d[7] vbloom reg3v3 scl porb
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 23/41 29 november 2000 sramvss 17 gnd in-column sram analog ground. vddcore/ reg3v3 34 pwr digital logic power. vddio 33 pwr digital pad ring power. vsscore 22 gnd digital logic ground. vssio 23 gnd digital pad ring ground. vid3v3 11 pwr on-chip video supply voltage regulator output aud3v3 3 pwr on-chip audio amplifier voltage regulator output analog signals vbloom 1 8 oa anti-blooming pixel reset voltage vbltw 2 7 oa bitline test white level reference vbg 1 oa internally generated bandgap reference voltage 1.22v vrt 3 2ia pixel reset voltage (nominally a monitor point but can be overdriven externally) vddhi 9 ia voltage doubler output, 4.6v -> 4.8v vbase 35 oa drive for base of external bipolar vbus 36 ia incoming power supply 3.3 -> 6v ain 4 ia analog input to audio amplifier aoutp 5 oa analog output of audio amplifier (positive) aoutn 6 oa analog output of audio amplifier (negative) porb 13 od power-on reset (bar) output. digital video interface d[4] d[3] d[2] d[1] d[0] 27 26 25 24 20 odt tri-stateable 5-wire output data bus. - d[4] is the most significant bit. - d[4:0] have programmable drive strengths 2, 4 and 6 ma qck 32 odt tri-stateable data qualification clock. lst/d[5] 28 odt tri-stateable line start output may be configured as tri-stateable output data bit 5 d[5]. fst/d[6] 29 odt tri-stateable frame start signal. may be configured as tri-stateable output data bit 6 d[6]. d[7] 31 odt tri-stateable data wire (ms data bit). may be configured as tri-stateable output data bit 6 d[6]. name pin number type description
STV0672-chipsetf-3-1.fm pinout and pin descriptions 29 november 2000 commercial in confidence 24/41 oeb 16 id digital output (tri-state) enable. digital control signals resetb 21 id system reset. active low. may be configured as system sync. active low. suspend 12 id usb suspend mode control signal. active high if this feature is not required then the support circuit must pull the pin to ground. the combination of an active high signal and pull up pad was chosen to limit current drawn by the device while in suspend mode. serial interface scl 15 bi serial bus clock (input only). sda 14 bi serial bus data (bidirectional, open drain). system clocks clki 30 id schmitt buffered clock input or lvds positive clock input 1. vbloom pin was bonded on pre-production samples but will not be bonded on production parts 2. vbltw pin was bonded on pre-production samples but will not be bonded on production parts 3. vrt pin was bonded on pre-production samples but will not be bonded on production parts key a analog input d digital input oa analog output id digital input with internal pull-up bi bidirectional id digital input with internal pull-down bi bidirectional with internal pull-up od digital output bi bidirectional with internal pull-down odt tri-stateable digital output name pin number type description
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 25/41 29 november 2000 5.2 vv6500 pin details figure 8 : 48 pin lcc package pin assignment name pin number type description power supplies avss 11 gnd core analog ground and reference supplies. resetb d[1] d[2] d[3] d[4] vbase vbus vbg vbloom vddhi vcmtcas nc oeb suspend 7 8 6 5 4 3 2 1 48 47 46 45 44 42 41 38 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 36 37 lst/d[5] fst/d[6] clki/clkip d[7] qck aud3v3 aoutp 40 39 18 30 31 43 vbltw d[0] aoutn sda porb vid3v3 avss ain vsscore vssio scl vddio nc nc nc nc nc nc nc sramvss vrt nc nc clkin nc reg3v3/vddcore nc
STV0672-chipsetf-3-1.fm pinout and pin descriptions 29 november 2000 commercial in confidence 26/41 sramvss 21 gnd in-column sram analog ground. vddio 43 pwr digital pad ring power. vsscore 29 gnd digital logic ground. vssio 30 gnd digital pad ring ground. sramvss 21 gnd in-column sram analogue ground. vddcore/ reg3v3 1 45 pwr digital logic power/regulated 3v3 digital supply vid3v3 12 pwr on-chip video supply voltage regulator output aud3v3 3 pwr on-chip audio amplifier voltage regulator output analog signals vbloom 2 8 oa anti-blooming pixel reset voltage vbltw 3 7 oa bitline test white level reference vbg 1 oa internally generated bandgap reference voltage 1.22v vcmtcas 13 ia common-mode input for column pre-amp. vrt 4 2 ia pixel reset voltage (nominally a monitor point but can be overdriven externally) vddhi 9 oa output from voltage doubler, 4.6v -> 4.8v vbase 46 oa drive for base of external bipolar vbus 47 ia incoming power supply 3.3v-> 6v ain 4 ia analog input to audio amplifier aoutp 5 oa analog output of audio amplifier (positive) aoutn 6 oa analog output of audio amplifier (negative) porb 16 oa power-on reset (bar) output. digital video interface d[4] d[3] d[2] d[1] d[0] 36 35 34 33 32 odt tri-stateable 5-wire output data bus. - d[4] is the most significant bit. - d[4:0] have programmable drive strengths 2, 4 and 6 ma qck 42 odt tri-stateable data qualification clock. clkin 40 bi lvds negative clock input lst/d[5] 37 odt tri-stateable line start output may be configured as tri-stateable output data bit 5 d[5]. name pin number type description
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 27/41 29 november 2000 fst/d[6] 38 odt tri-stateable frame start signal. may be configured as tri-stateable output data bit 6 d[6]. d[7] 41 odt tri-stateable data wire (ms data bit). may be configured as tri-stateable output data bit 6 d[6]. oeb 20 id digital output (tri-state) enable. digital control signals resetb 31 id system reset. active low. may be configured as system sync. active low. suspend 15 id usb suspend mode control signal. active high if this feature is not required then the support circuit must pull the pin to ground. the combination of an active high signal and pull up pad was chosen to limit current drawn by the device while in suspend mode. serial interface scl 18 bi serial bus clock (input only). sda 17 bi serial bus data (bidirectional, open drain). system clocks clki/clkip 39 id schmitt buffered clock input or lvds positive clock input clkin 40 id lvds negative clock input 1. pre production samples of this device had reg3v3 and vddcore bonded out separately. the production version of the device will have reg3v3 and vddcore common bonded out to pin 45. there will be no requirement to change any support design/pcbs as the two signals from pin 44 and pin 45 were connected together on the ref- erence design. 2. vbloom pin was bonded on pre-production samples but will not be bonded on production parts 3. vbltw pin was bonded on pre-production samples but will not be bonded on production parts 4. vrt pin was bonded on pre-production samples but will not be bonded on production parts key a analog input d digital input oa analog output id digital input with internal pull-up bi bidirectional id digital input with internal pull-down bi bidirectional with internal pull-up od digital output bi bidirectional with internal pull-down odt tri-stateable digital output name pin number type description
STV0672-chipsetf-3-1.fm pinout and pin descriptions 29 november 2000 commercial in confidence 28/41 5.3 STV0672 pin details pin signal type description power supplies 1 test_cf0 input test con?uration bit - connect to vdd for normal operation 2 test_cf1 input test con?uration bit - connect to vdd for normal operation 3 test_cf2 input test con?uration bit - connect to vdd for normal operation 4 pll_vdd input vdd for internal phase locked loop 5 pll_gnd input gnd for internal phase locked loop 8 core_vdd input vdd for core logic 9 core_vss input ground for core logic 10 io_vdd input vdd for pad ring 11 io_vss input ground for pad ring 22 io_vdd input vdd for pad ring 23 io_vss input ground for pad ring microport_5 microport_3 microport_2 microport_1 microport_0 io_vdd switch_int_n io_vdd core_gnd test_conf1 usb_dp eeprom_sda eeprom_scl usb_dn pll_vdd pll_gnd xtal_in xtal_out core_gnd io_vdd io_gnd digiport_9 reset_n microport_7 microport_6 microport_4 io_gnd microport_12 xxxx_int_n ssda sscl io_gnd digiport_5 core_vdd test_conf0 test_conf2 spdn core_vdd microport_11 io_gnd microport_9 microport_8 digiport_7 digiport_8 digiport_6 microport_14 microport_13 microport_10 digiport_4 digiport_3 digiport_2 digiport_1 digiport_0 io_vdd io_gnd core_vdd core_gnd sensor_clk sensor_db5 sensor_db4 sensor_db3 sensor_db2 sensor_db1 sensor_db0 1 17 16 32 33 48 49 64 figure 9 : cpia 2 pinout - packaged in 64 tqfp
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 29/41 29 november 2000 24 core_vdd input vdd for core logic 25 core_vss input ground for core logic 39 io_vdd input vdd for pad ring 40 io_vss input ground for pad ring 49 io_vss input ground for pad ring 57 core_vdd input vdd for core logic 58 core_vss input ground for core logic 59 io_vdd input vdd for pad ring 60 io_vss input ground for pad ring device master clock and reset 6 xtal_in ana system clock pad 7 xtal_out osc system clock pad 33 reset_n schmitt system, power-on-reset supplied by companion sensor digiport/usb config interface 12 digiport_9 1 bidir unused (leave unconnected) 2 13 digiport_8 bidir unused (connect to vss) 14 digiport_7 bidir programmable usb vendor id 15 digiport_6 bidir programmable usb vendor id 16 digiport_5 bidir programmable usb vendor id 17 digiport_4 bidir programmable usb vendor id 18 digiport_3 bidir programmable usb vendor id 19 digiport_2 bidir programmable usb vendor id 20 digiport_1 bidir programmable usb vendor id 21 digiport_0 bidir programmable usb vendor id sensor interface 26 sensor_clk bidir vv6410/vv6500 sensor clock 27 sensor_db5 bidir vv6410/vv6500 sensor data bus [bit5] 28 sensor_db4 bidir vv6410/vv6500 sensor data bus [bit4] 29 sensor_db3 bidir vv6410/vv6500 sensor data bus [bit3] 30 sensor_db2 bidir vv6410/vv6500 sensor data bus [bit2] 31 sensor_db1 bidir vv6410/vv6500 sensor data bus [bit1] 32 sensor_db0 bidir vv6410/vv6500 sensor data bus [bit0] 34 ssda 3 state vv6410/vv6500 sensor serial interface data 35 sscl 3 state vv6410/vv6500 sensor serial interface clock 36 spdn bidir control line to sensor to select ultra low power suspend mode misc control 37 xx_int input remote wakeup 38 switch_int input load twain driver data upload microport/gpio interface 41 microport_0 3 bidir general purpose input/output (gpio) pin signal type description
STV0672-chipsetf-3-1.fm pinout and pin descriptions 29 november 2000 commercial in confidence 30/41 42 microport_1 bidir general purpose input/output (gpio) 43 microport_2 bidir general purpose input/output (gpio) 44 microport_3 bidir general purpose input/output (gpio) 45 microport_4 bidir general purpose input/output (gpio) 46 microport_5 bidir general purpose input/output (gpio) 47 microport_6 bidir general purpose input/output (gpio) 48 microport_7 bidir general purpose input/output (gpio) 50 microport_8 4 bidir vdd 51 microport_9 bidir vss 52 microport_10 bidir vdd 53 microport_11 bidir vdd 54 microport_12 bidir vdd 55 microport_13 bidir vss 56 microport_14 bidir vss usb interface 61 usb_dn bidir usb data line 62 usb_dp bidir usb data line eeprom interface 63 eeprom_sda bidir serial data to/from the eeprom 64 eeprom_scl output serial clock to the eeprom 1. the digiport pins can be recon?ured, please contact stmicroelectronics for more details on this feature 2. bit[9] of the digiport is connected to vdd in current reference design. this is incorrect and should be left unconnected to ensure that no extra supply current is drawn. 3. the microport bus can be recon?ured, please contact stmicroelectronics for more details on this feature 4. bit8 of the microport can enable extra device functionality, please contact stmicroelectronics for more details on this feature. pin signal type description
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 31/41 29 november 2000 6. package details 6.1 vv6410 (36pin clcc) revno revision note date 2 1 3 4 5 6 78 ecn no. 10.67 - 0.13 +0.30 2.67 2.02 8.13 0.13 1.02 0.13 40 places r 0.15 notes. 1. die is optically centred. 2. refractive index of glass is ~1.52. 3. distance to optical surface of die. 4. pixel area of sensor. pin 1 pin 5 pin 6 a a 1.16 0.09 (note 3) 2.15 - 0.26 +0.16 0.60 - 0.10 0.00 1.55 0.16 a-a (8 : 1) a pin locations changed, tolerance added to o/all dims 14/7/99 b package now 36 pin 20/7/99 c 1.03 0.13 was 1.03 0.08 2/8/99 d 1.16 dim tolerance revised 15/10/99
STV0672-chipsetf-3-1.fm package details 29 november 2000 commercial in confidence 32/41 6.2 vv6500 (48pin clcc) 14.52 14.09 4.83 (note 4) 3.63 (note 4) r 0.15 , 48 places 11.18 0.13 1.02 0.13 13.70 n o t es. 1. die is optically centred. 2. refractive index of glass is ~1.52. 3. distance to optical surface of die. 4. pixel area of sensor. pin 1 pin 6 pin 7 a a 2.34 1.91 1.71 1.39 1.21 1.09 0.60 0.50 a-a
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 33/41 29 november 2000 6.3 STV0672 (64pin tqfp) figure 10 : STV0672 package details
STV0672-chipsetf-3-1.fm vv6410/vv6500+STV0672 reference design 29 november 2000 commercial in confidence 34/41 7. vv6410/vv6500+STV0672 reference design stmicroelectronics will make a reference design available for the vv6410/vv6500+STV0672 chipset. contact stmicroelectronics for more details. the schematics describing the reference design are included over the following 4 pages of the datasheet
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 35/41 29 november 2000
STV0672-chipsetf-3-1.fm vv6410/vv6500+STV0672 reference design 29 november 2000 commercial in confidence 36/41
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 37/41 29 november 2000
STV0672-chipsetf-3-1.fm reference design and evaluation kits (rdk? and evk?) 29 november 2000 commercial in confidence 38/41 8. reference design and evaluation kits (rdks and evks) stmicroelectronics supply a full range of supporting reference design kits for their range of sensors and coprocessors. the stv- usb /vga-r01 (comprising the STV0672 coprocessor and the 6500 vga resolution sensor) and stv-usb/cif-r01 (comprising the STV0672 coprocessor and the 6410 cif resolution sensor) reference design kits allow direct interface to a pc via the usb port. a full evaluation kit for the usb camera chipset will also be available in the future. please contact stmicroelectronics for mo re details on this product. please contact stmicroelectronics for more details on how to order these support products.
customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm commercial in confidence 39/41 29 november 2000 9. design issues the pcb gerbers that are included in the documentation package that accompanies the reference design kit shows the sensor and the coprocessor on the same side of the pcb. although this placement of the ic? will not give the smallest physical design it will avoid any excess heat being transferred from STV0672 to the sensors. excess heat in the sensor is a source of noise that will degrade the image performance, especially in low light. stmicroelectronics therefore recommends that the ?ide-by-side?orientation of STV0672 and 6410/6500 should be followed if the design is to achieve optimal image performance under a wide range of lighting conditions.
STV0672-chipsetf-3-1.fm ordering details 29 november 2000 commercial in confidence 40/41 10. ordering details for more information on the appropriate sensor choice please contact stmicroelectronics . part number description vv6410c036 cif image sensor, 36clcc package vv6500c001 vga image sensor, 48clcc package STV0672 companion usb co-processor stv-usb/cif-r01 usb chipset, cif resolution reference design kit stv-usb/vga-r01 usb chipset, vga resolution reference design kit table 15 : ordering details
commercial in confidence 41/41 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics the st logo is a registered trademark of stmicroelectronics ?2000 stmicroelectronics - all rights reserved imaging divison 29 november 2000 customer datasheet, rev 3.1, 29 november 2000 STV0672-chipsetf-3-1.fm www.st.com asiapacific.imaging@st.com centraleurope.imaging@st.com france.imaging@st.com japan.imaging@st.com nordic.imaging@st.com southerneurope.imaging@st.com ukeire.imaging@st.com usa.imaging@st.com

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